The present invention relates generally to dielectric isolated substrates and more specifically to method for forming ultra-thin dielectrically isolated wafers.
One common method of forming dielectrically isolated integrated circuit wafers is illustrated in FIGS. 1A through 1D. A semiconductor wafer 10 having a thickness generally in the range of 19 to 26 mils has grooves 12 etched in a first surface 14. The wafer 10 generally is selected such that the etch is anisotropic. The first surface 14 and moats 12 is then covered with a layer of dielectrical isolation 16. A polycrystalline support 18 is then formed over the dielectric isolation 16 and generally has a thickness in the range of 20 to 30 mils. The wafer 10 is then reduced by grinding from a second surface 20 until it intersects the dielectric isolation layer 16 to produce dielectric isolated regions 10 at a third surface 22. This process illustrated FIGS. 1A through 1D. The resulting dielectric isolation islands 10 have thickness in the range of the 10 to 40 microns and the total thickness of the wafer from the surface 22 to surface 24 of the polycrystalline support 18 is in the range of 19 to 26 mils. Device forming steps are then performed on surface 22 and the wafer shown is then used.
Although the process described above is now in common practice in the industry, earlier manufacturing processes had problems in developing a thick polycrystalline support 18. As a solution to this problem, Jordan, in U.S. Pat. No. 3,689,357 only provided a very thin polycrystalline layer in the one to two mil thickness range which did not over fill the moats. Then the moats were filled with fusing glass to be used to bond to a monocrystalline wafer to the polycrystalline support. This combined structure provided the appropriate support structure. The monocrystalline wafer was in the range of 10 mils.
There is substantial interest in a process to form ultra-thin wafers in the range below 7 mils. The processes of the prior art have not address the problem of forming such a thin wafer.
Thus it is a object of the present invention to provide a process for producing ultra-thin wafers having dielectric isolated integrated circuits therein.
Still another object of the present invention is to provide a method of fabricating ultra-thin dielectrically isolated circuits compatible with present processing technology. These and other objects are achieved by filling etched moats with a first dielectric layer and a first layer of polycrystalline material and planarizing. A second dielectric layer is formed on the first polycrystalline layer and a second layer of polycrystalline is formed on the second dielectric layer to form a handle. The starting material is then thinned to produce the dielectric isolated islands. Device forming step are then performed. Finally, the handle is removed leaving a wafer having a thickness defined by the planarized surface of the first polycrystalline layer and the top surface of the first wafer. The planarization and thinning produce a resulting wafer having a thickness below 7 mils. Removing the handle includes grinding the handle for a substantial portion of the handle thickness and etching the remainder of the handle using the second dielectric layer as an etch stop.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.